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  1. Esterel EDA

    ESL-to-RTL synthesis for control-intensive IP design and verification.
    RTL2
    VHDL1
    Verilog1
    code generation1
    SystemC1
    formal methods1
    correct by construction1
    ESL synthesis1
    automated implementation1
    Electronic System Level1
    unambiguous specifications1
    Esterel Studio0

    www.esterel-eda.com - 2009-02-09

  2. Space Codesign System Inc., Codesign your FPGA now !

    --> Bientôt en -------------------------------------------------------------------------------------------------------------------------------------------- ...
    software7
    real7
    hardware4
    system4
    time3
    design services2
    ESL2
    operating2
    RTOS1
    design consulting1
    Algorithmic1
    SystemC1
    codesign1
    Performance Modeling1
    Architecture Analysis1
    electronic system level1
    partitionning1

    spacecodesign.grm.polymtl.ca - 2009-04-02

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